1. Field of the Invention
The present invention relates to a layout structure for chip coupling, and more particularly to a layout structure that can ensure an electrical connection with a chip and thereby reduce the chip size, under the precision of the conventional machine.
2. Descriptions of the Related Art
Liquid crystal displays (LCDs) have replaced conventional displays and become mainstream products due to their low power consumption, light weight, low radiation and portability. In addition to key parts, such as a backlight module, liquid crystals and a color filter, an integrated circuit (IC) chip and a layout structure of the display panel are provided for converting external signals into control signals to control the luminance of each pixel.
In a conventional LCD 10, as depicted in FIG. 1, a layout structure 13 is formed on a glass substrate 11. An IC chip 15 is disposed at the lowermost edge of the glass substrate 11 to electrically connect with the layout structure 13 and connect to a flexible printed circuit (FPC) 17 on the other side. During operation, external signals are transferred through the FPC 17 to the IC chip 15 and are converted into control signals to control the luminance of each pixel through the layout structure 13.
The most common conventional technology used for bonding the IC chip 15 to the glass substrate 11 is the chip on glass (COG) technology. By the COG technology, the IC chip 15 with bumps is directly bonded onto the layout structure 13 of the glass substrate 11. FIGS. 2A and 2B illustrate two partially enlarged schematic views of the layout structure 13 disposed on the glass substrate 11 and connected with the IC chip 15. The layout structure 13 comprises a plurality of lines 131 and a plurality of conductive pads 133 corresponding to the bumps on the IC chip 15. When the IC chip 15 is overlaid onto the layout structure 13, the bumps of the IC chip 15 will be correspondingly bonded with the conductive pads 133 of the layout structure 13 to establish an electrical conduction state therebetween through the conductive particles.
However, there are still issues with the aforesaid structure. Still referring to FIGS. 2A and 2B, a conventional conductive pad layout design for dual-line routing is depicted in FIG. 2A, while a conventional conductive pad layout design for triple-line routing is depicted in FIG. 2B. Typically, in conventional technology, the conductive pads 133 are approximately the same in size as the bumps of the IC chip 15 so that the bumps can come into contact exactly with the conductive pads 133 after the bonding process. However, if the preciseness of the machine is not enough, the bumps may shift from the desired position. Such a shift will lead to a reduced contact area between the bumps and the conductive pads 133, thus, making the electrical conductivity therebetween inadequate. Furthermore, such bumps may come into contact with adjacent lines 131, eventually leading to short-circuits or product failures.
Consequently, in conventional technology, an adequate spacing is maintained between the conductive pads 133 and their adjacent lines 131 to prevent the bumps from coming into contact with the adjacent lines 131 due to the IC chip 15 shift during the bonding process. During the manufacturing process, a finer spacing between the individual lines 131 or between the individual conductive pads 133 is preferred to reduce the size of the final product. However, if there is a shift during the chip bonding process, then a large spacing between the conductive pads 133 and the adjacent lines 131 would be preferred. Thus, these two objectives contradict each other, making it difficult for the designers to account for both situations. In addition, the spacing maintained between the conductive pads 133 and the lines 131 is estimated according to the machine precision, the inaccuracy of the feed materials or the process stability criteria evaluated by the manufacturers. Thus, the machine precision, the inaccuracy of the feed materials or the process stability criteria evaluated by the manufacturers will also affect the IC chip 15 design dimensions.
In the conventional process, the IC chip 15 has to be made with excessive footprints, which causes the display area to shrink correspondingly, due to the limitations of the stability and manufacturing capability of the bonding machine. As a result, the IC chip 15 is undesirable for the miniaturization of the LCD products. On the contrary, if a smaller IC chip 15 is desired for the LCD, a bonding machine of higher precision will become a necessity, which will increase the manufacturing cost of the LCD.
Given the above, a novel layout structure that meets the manufacturing process criteria under the precision of conventional bonding machines needs to be developed in this field.